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FBDVerifier: Interactive and Visual Analysis of Counterexample in Formal Verification of Function Block Diagram
Function Block Diagram Formal Verification Counter-example Visualization Verilog Translation Programmable Logic Controller Model Checking
2014/3/11
Model checking is often applied to verify safety-critical software implemented in programmable logic controller (PLC) language such as a function block diagram (FBD). Counter-examples generated by a m...
Empirical Evaluation and Review of a Metrics–Based Approach for Use Case Verification
Empirical Evaluation Review of a Metrics–Based Approach Case Verification
2014/3/12
In this article, an empirical evaluation and review of some metrics–based verification heuristics for use cases are presented. This evaluation is based on empirical data collected from requirements do...